LTC3416
1
3416f
s
High Efficiency: Up to 95%
s
4A Output Current
s
Low R
DS(ON)
Internal Switch: 67m
s
Tracking Input to Provide Easy Supply Sequencing
s
Programmable Frequency: 300kHz to 4MHz
s
2.25V to 5.5V Input Voltage Range
s
2% Output Voltage Accuracy
s
0.8V Reference Allows Low Output Voltage
s
Low Dropout Operation: 100% Duty Cycle
s
Power Good Output Voltage Monitor
s
Overtemperature Protected
s
Available in a 20-Lead Thermally Enhanced
TSSOP Package
4A, 4MHz, Monolithic
Synchronous Step-Down
Regulator with Tracking
s
Portable Instruments
s
Notebook Computers
s
Distributed Power Systems
s
Battery-Powered Equipment
s
POL Board Power
SVIN
PGOOD
22
F
V
OUT2
2.5V
100
F
2
V
OUT1
1.8V
4A
0.2
H
SW
LTC3416
PGND
SGND
R
T
RUN/SS
I
TH
TRACK
PVIN
V
FB
127k
7.5k
200k
255k
200k
255k
3416 F01a
820pF
V
IN
2.5V TO 5.5V
I/O VOLTAGE
Figure 1a. 2.5V/4A Step-Down Regulator with Tracking
The LTC
3416 is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage from 0.8V to 5V while delivering
up to 4A of output current. The internal synchronous
power switch with 67m
of on-resistance increases effi-
ciency and eliminates the need for an external Schottky
diode. Switching frequency is set by an external resistor.
100% duty cycle provides low dropout operation extend-
ing battery life in portable systems. OPTI-LOOP
compen-
sation allows the transient response to be optimized over
a wide range of loads and output capacitors.
The LTC3416 operates in forced continuous operation and
provides tracking of another power supply rail. Forced
continuous operation reduces noise and RF interference and
provides excellent transient response. Fault protection is
provided by an overcurrent comparator, and adjustable
compensation allows the transient response to be optimized
over a wide range of loads and output capacitors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
Figure 1b. Efficiency vs Load Current
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.10
1
10
3416 G09
30
20
10
0
90
100
V
IN
= 2.5V
V
OUT
= 1.8V
f = 2MHz
V
IN
= 3.3V
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
LTC3416
2
3416f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Input Voltage Range
2.25
5.5
V
V
FB
Regulated Feedback Voltage
(Note 3)
q
0.784
0.800
0.816
V
I
FB
Feedback Input Current
0.2
A
V
FB
Reference Voltage Line Regulation
V
IN
= 2.5V to 5.5V (Note 3)
0.04
0.2
%/V
V
TRACK
Tracking Voltage Offset
V
TRACK
= 0.4V
30
mV
Tracking Voltage Range
0
0.8
V
V
LOADREG
Output Voltage Load Regulation
Measured in Servo Loop, V
ITH
= 0.36V
0.02
0.2
%
Measured in Servo Loop, V
ITH
= 0.84V
0.02
0.2
%
V
PGOOD
Power Good Range
7.5
9
%
R
PGOOD
Power Good Resistance
120
200
I
Q
Input DC Bias Current
(Note 4)
Active Current
V
FB
= 0.7V, V
ITH
= 1.2V
300
350
A
Shutdown
V
RUN
= 0V
0.02
1
A
f
OSC
Switching Frequency
R
OSC
= 294k
0.88
1
1.12
MHz
Switching Frequency Range
0.30
4.00
MHz
f
SYNC
SYNC Capture Range
0.3
4
MHz
R
PFET
R
DS(ON)
of P-Channel FET
I
SW
= 300mA
67
100
m
R
NFET
R
DS(ON)
of N-Channel FET
I
SW
= 300mA
50
100
m
I
LIMIT
Peak Current Limit
6
8
A
V
UVLO
Undervoltage Lockout Threshold
1.75
2
2.25
V
I
LSW
SW Leakage Current
V
RUN
= 0V, V
IN
= 5.5V
0.1
1
A
V
RUN
RUN Threshold
0.5
0.65
0.8
V
Input Supply Voltage .................................. 0.3V to 6V
I
TH
, RUN, V
FB
Voltages .............................. 0.3V to V
IN
TRACK Voltage .......................................... 0.3V to V
IN
SW Voltage .................................. 0.3V to (V
IN
+ 0.3V)
Peak SW Sink and Source Current ......................... 11A
Operating Ambient Temperature Range
(Note 2) .................................................. 40
C to 85
C
Junction Temperature (Notes 5, 6) ...................... 125
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
ORDER PART
NUMBER
(Note 1)
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTC3416EFE
T
JMAX
= 125
C,
JA
= 38
C/W,
JC
= 10
C/W
EXPOSED PAD IS GND (PIN 21)
MUST BE SOLDERED TO PCB
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
IN
= 3.3V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
PGND
R
T
TRACK
RUN/SS
SGND
NC
PV
IN
SW
SW
PGND
PGND
V
FB
I
TH
PGOOD
SV
IN
NC
PV
IN
SW
SW
PGND
21
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3416E is guaranteed to meet performance specifications
from 0
C to 70
C. Specifications over the 40
C to 85
C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3416 is tested in a feedback loop that adjusts V
FB
to
achieve a specified error amplifier output voltage (I
TH
).
LTC3416
3
3416f
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
as follows:
LTC3416E: T
J
= T
A
+ (P
D
)(38
C/W)
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Switch On-Resistance
vs Input Voltage
TEMPERATURE (
C)
40
0.795
V
REF
(V)
0.796
0.798
0.799
0.800
0
40
60
140
3416 G01
0.797
20
20
80 100 120
INPUT VOLTAGE (V)
2.25 2.75 3.25
3.75
4.25 4.75
5.25
5.75
ON-RESISTANCE (m
)
90
80
70
60
50
40
30
20
10
0
3416 G02
PFET
NFET
T
A
= 25
C
TEMPERATURE (
C)
40
ON-RESISTANCE (m
)
120
100
80
60
40
20
0
25
3416 G03
10 5 20 35 50 65 80 95 110 125
PFET
NFET
V
REF
vs Temperature, V
IN
= 3.3V
Switch On-Resistance
vs Temperature, V
IN
= 3.3V
Switch Leakage vs Input Voltage
INPUT VOLTAGE (V)
2.25
SWITCH LEAKAGE CURRENT (nA)
20
18
16
14
12
10
8
6
4
2
0
3.25
4.25
4.75
3416 G04
2.75
3.75
5.25
PFET
NFET
T
A
= 25
C
Frequency vs R
OSC
R
OSC
(k)
25
FREQUENCY (kHz)
7000
6000
5000
4000
3000
2000
1000
0
3416 G05
225
925
825
725
625
525
125
325 425
V
IN
= 3.3V
T
A
= 25
C
Frequency vs Input Voltage
INPUT VOLTAGE (V)
2.25
3.25
4.25
4.75
2.75
3.75
5.25
1040
1020
1000
980
960
940
920
900
3416 G06
FREQUENCY (kHz)
R
OSC
= 294k
T
A
= 25
C
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125
C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
LTC3416
4
3416f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
DC Supply Current
vs Input Voltage
Frequency vs Temperature
Efficiency vs Load Current,
Forced Continuous
TEMPERATURE (
C)
40
60
1090
1070
1050
1030
1010
990
970
950
930
910
3416 G07
20
120
0
20
40
80
100
FREQUENCY (kHz)
V
IN
= 3.3V
R
OSC
= 294k
INPUT VOLTAGE (V)
2.25
400
350
300
250
200
150
100
50
0
3.75
4.75
3416 G08
2.75
3.25
4.25
5.25
QUIESCENT CURRENT (
A)
Load Step Transient
Efficiency vs Input Voltage
INPUT VOLTAGE (V)
2.5
EFFICIENCY (%)
3.0
3.5
4.0
4.5
3416 G10
5.0
98
96
94
92
90
88
86
84
82
80
78
5.5
I
OUT
= 1A
I
OUT
= 4A
V
OUT
= 2.5V
T
A
= 25
C
Load Regulation
LOAD CURRENT (A)
V
OUT
/V
OUT
(%)
3416 G11
0
0.20
0.40
0.60
0.80
1.00
1.20
1.40
0
1.0
2.0
2.5
0.5
1.5
3.0
3.5
4.0
V
IN
= 3.3V
V
OUT
= 1.8V
3416 G12
V
IN
= 3.3V, V
OUT
= 1.8V
f = 2MHz
LOAD STEP = 0A TO 4A
V
OUT
INDUCTOR
CURRENT
2A/DIV
20
s/DIV
3416 G13
V
IN
= 3.3V, V
OUT
= 1.8V
TRACKING 2.5V
5ms/DIV
Tracking: Start-Up and Shutdown
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.10
1
10
3416 G09
30
20
10
0
90
100
V
IN
= 2.5V
V
IN
= 3.3V
V
OUT
= 1.8V
f = 2MHz
LTC3416
5
3416f
U
U
U
PI FU CTIO S
PGND (Pins 1, 10, 11, 20): Power Ground. Connect this
pin closely to the () terminal of C
IN
and C
OUT
.
R
T
(Pin 2): Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
TRACK (Pin 3): Tracking Voltage Input. Applying a voltage
that is less than 0.8V to this pin enables tracking. During
tracking, the V
FB
pin will regulate to the voltage on this pin.
Do not float this pin.
RUN/SS (Pin 4): Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3416. In shutdown
all functions are disabled, drawing <1
A of supply current.
A capacitor to ground from this pin sets the ramp time to
full output current.
SGND (Pin 5): Signal Ground. All small-signal compo-
nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
NC (Pins 6, 15): No Connect.
PV
IN
(Pins 7, 14): Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 8, 9, 12, 13): Switch Node Connection to
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
SV
IN
(Pin 16): Signal Input Supply. Decouple this pin to
the SGND capacitor.
PGOOD (Pin 17): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage is
not within
7.5% of the regulation point.
I
TH
(Pin 18): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V to
1.4V with 0.4V corresponding to the zero-sense voltage
(zero current).
V
FB
(Pin 19): Feedback Pin. Receives the feedback voltage
from a resistive divider connected across the output.
Exposed Pad (Pin 21): Ground. Connect to SGND.
LTC3416
6
3416f
FU CTIO AL DIAGRA
U
U
W
+
+
+
+
19
ERROR
AMPLIFIER
0.74V
V
FB
3
TRACK
SV
IN
4
RUN/SS
17
PGOOD
RUN
0.86V
+
VOLTAGE
REFERENCE
SLOPE
COMPENSATION
OSCILLATOR
R
T
LOGIC
SLOPE
COMPENSATION
RECOVERY
PMOS CURRENT
COMPARATOR
NMOS CURRENT
COMPARATOR
16
SGND
5
EXPOSED
PAD
21
I
TH
18
SW
PGND
3416 FD
8
PV
IN
7
14
9
12
13
1
10
11
20
2
OPERATIO
U
Main Control Loop
The LTC3416 is a monolithic, constant frequency, current
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the I
TH
pin.
The error amplifier adjusts the voltage on the I
TH
pin by
comparing the feedback signal from a resistor divider on
the V
FB
pin with an internal 0.8V reference. When the load
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the I
TH
voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at 5A.
The operating frequency is externally set by an external
resistor connected between the R
T
pin and ground. The
practical switching frequency can range from 300kHz to
4MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by
7.5%. In an overvoltage condition, the top
LTC3416
7
3416f
OPERATIO
U
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET's current limit is reached.
Voltage Tracking
Some microprocessors, ASIC and DSP chips need two
power supplies with different voltage levels. These sys-
tems often require voltage sequencing between the core
power supply and the I/O power supply. Without proper
sequencing, latch-up failure or excessive current draw
may occur that could result in damage to the processor's
I/O ports or the I/O ports of supporting system devices
such as memory, FPGAs or data converters. To ensure
that the I/O loads are not driven until the core voltage is
properly biased, tracking of the core supply voltage and
the I/O supply voltage is necessary.
Voltage tracking is enabled by applying a voltage to the
TRACK pin. When the voltage on the TRACK pin is below
0.8V, the feedback voltage will regulate to this tracking
voltage. When the tracking voltage exceeds 0.8V, tracking
is disabled and the feedback voltage will regulate to the
internal reference voltage.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle, eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3416 is designed to operate down to an input
supply voltage of 2.25V. One important consideration at
low input supply voltages is that the R
DS(ON)
of the
P-channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3416 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3416, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current exceeds 7.8A, the top power
MOSFET will be held off and switching cycles will be
skipped until the inductor current is reduced.
LTC3416
8
3416f
APPLICATIO S I FOR ATIO
W
U
U
U
The basic LTC3416 application circuit is shown in Figure 1a.
External component selection is determined by the maxi-
mum load current and begins with the selection of the
operating frequency and inductor value followed by C
IN
and C
OUT
.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3416 is determined by
an external resistor that is connected between the R
T
pin
and ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
R
f
k
OSC
=
( )
3 08 10
10
11
.
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3416 imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns. Therefore, the minimum duty cycle is
equal to 100 110ns f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current
I
L
increases with higher V
IN
or lower V
OUT
and decreases with higher inductance.
=
I
V
fL
V
V
L
OUT
OUT
IN
1
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is
I
L
= 0.4(I
MAX
). The largest ripple current occurs at the
highest V
IN
. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
L
V
f I
V
V
OUT
L MAX
OUT
IN MAX
=
(
)
(
)
1
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates "hard," which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don't radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar characteristics. The choice of which style inductor
to use mainly depends on the price vs size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Coiltronics,
Coilcraft, Toko and Sumida.
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the trapezoi-
dal wave current at the source of the top MOSFET. To
LTC3416
9
3416f
APPLICATIO S I FOR ATIO
W
U
U
U
prevent large voltage transients from occurring, a low ESR
input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
I
I
V
V
V
V
RMS
OUT MAX
OUT
IN
IN
OUT
=
(
)
1
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, or choose a capacitor rated at a higher tempera-
ture than required. Several capacitors may also be paral-
leled to meet size or height requirements in the design. For
low input voltage applications, sufficient bulk input ca-
pacitance is needed to minimize transient effects during
output load changes.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple,
V
OUT
, is determined by:
+
V
I ESR
fC
OUT
L
OUT
1
8
The output ripple is highest at maximum input voltage
since
I
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special poly-
mer, aluminum electrolytic and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capaci-
tors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
V
IN
. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at V
IN
large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
V
V
R
R
OUT
=
+
0 8
1
2
1
.
The resistive divider allows the V
FB
pin to sense a fraction
of the output voltage as shown in Figure 2.
Figure 2. Setting the Output Voltage
LTC3416
SGND
R1
3416 F02
R2
V
FB
V
OUT
Voltage Tracking
The LTC3416 allows the user to program how its output
voltage ramps during start-up by means of the TRACK pin.
Through this pin, the output voltage can be set up to either
LTC3416
10
3416f
APPLICATIO S I FOR ATIO
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coincidentally or ratiometrically track another output volt-
age as shown in Figure 3.
If the voltage on the TRACK pin is less than 0.8V, voltage
tracking is enabled. During voltage tracking, the output
voltage regulates to the tracking voltage through a resistor
divider network. The output voltage during tracking can be
calculated with the following equation:
V
V
R
R
OUT
TRACK
=
+
1
2
1
, V
TRACK
< 0.8V
Voltage tracking can be accomplished by sensing a frac-
tion of the output voltage from another regulator. This is
typically done by using a resistor divider to attenuate the
output voltage that is being tracked. Setting this attenua-
tion factor equal to the reciprocal of the gain factor
provided by the feedback resistors will force the regulator
outputs to be equal to each other during tracking. If
tracking is not desired, connect the TRACK pin to SV
IN
.
To implement the coincident tracking shown in Figure 3a,
connect an extra resistor divider to the output of V
OUT2
and
connect its midpoint to the TRACK pin of the LTC3416 as
shown in Figure 4. The ratio of this divider should be
selected the same as that of V
OUT1
's resistor divider. To
implement the ratiometric sequencing in Figure 3b, no
extra resistor divider is necessary. Simply connect the
TRACK pin to V
FB(MASTER)
.
An alternative method of tracking is shown in Figure 5. For
the circuit of Figure 5, the following equations can be used
to determine the resistor values:
V
V
R
R
V
V
R
R
R
R
R
V
V
OUT
OUT
OUT
OUT
1
2
2
1
0 8
1
2
1
0 8
1
4
5
3
4
3
1
=
+
=
+
+
=
.
.
TIME
(3a) Coincident Tracking
V
OUT2
V
OUT1
OUTPUT VOLTAGE
TIME
3416 F03
(3b) Ratiometric Sequencing
V
OUT2
V
OUT1
OUTPUT VOLTAGE
Figure 3. Two Different Modes of Output Voltage Sequencing
R4
R2
R3
R1
(4a) Coincident Tracking Setup
TO
V
FB(MASTER)
PIN
TO
TRACK
PIN
V
OUT2
R2
R1
3416 F04
(4b) Ratiometric Setup
TO
V
FB(MASTER)
PIN
TO
TRACK
PIN
V
OUT2
Figure 4. Setup for Tracking and Ratiometric Sequencing
LTC3416
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APPLICATIO S I FOR ATIO
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Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3416 as well as a timer for soft-start. Pulling the RUN/
SS pin below 0.5V places the LTC3416 in a low quiescent
current shutdown state (I
Q
< 1
A).
The soft-start gradually raises the clamp on I
TH
. The full
current range becomes available on I
TH
after the voltage
on I
TH
reaches approximately 2V. The clamp on I
TH
is set
externally with a resistor and capacitor on the RUN/SS pin
as shown in Figure 1a. The soft-start duration can be
calculated by using the following formula:
t
R C In
V
V
V
Seconds
SS
SS SS
IN
IN
=
.
(
)
1 8
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
The V
IN
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger
than the DC bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is "chopped" between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
In most applications, the LTC3416 does not dissipate
much heat due to its high efficiency. But in applications
where the LTC3416 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
Figure 5. Dual Voltage System with Tracking
LTC3416
SGND
R1
3416 F05
R2
V
FB
TRACK
V
OUT1
LTC3416
SLAVE
MASTER
SGND
R3
R4
R5
V
FB
V
OUT2
LTC3416
12
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APPLICATIO S I FOR ATIO
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in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150
C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC3416 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(
JA
)
where P
D
is the power dissipated by the regulator and
JA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 20-lead exposed TSSOP
package, the
JA
is 38
C/W.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
To maximize the thermal performance of the LTC3416, the
Exposed Pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
When a load step occurs, V
OUT
immediately shifts by an
amount equal to
I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components and output capaci-
tor shown in figure 1a will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3416 in an
application with the following specifications: V
IN
= 3.3V,
V
OUT1
= 1.8V, V
OUT2
= 2.5V, I
OUT1(MAX)
= I
OUT2(MAX)
= 4A,
f = 1MHz. V
OUT1
and V
OUT2
must track when powering up
and powering down.
First, calculate the timing resistor:
R
k
k
OSC
=
=
3 08 10
1 10
10
298
11
6
.
Use a standard value of 294k
. Next, calculate the induc-
tor values for about 40% ripple current:
L
V
MHz
A
V
V
H
L
V
MHz
A
V
V
H
1
1 8
1
1 6
1
1 8
3 3
0 51
2
2 5
1
1 6
1
2 5
3 3
0 38
=
=
=
=
.
.
.
.
.
.
.
.
.
.
Using a 0.47
H inductor for both results in maximum
ripple currents of:
=
=
=
=
I
V
MHz
H
V
V
A
I
V
MHz
H
V
V
A
L
L
1
2
1 8
1
0 47
1
1 8
3 3
1 74
2 5
1
0 47
1
2 5
3 3
1 29
.
.
.
.
.
.
.
.
.
.
C
OUT1
and C
OUT2
will be selected based on the ESR that is
required to satisfy the output voltage ripple requirement
and the bulk capacitance needed for loop stability. For this
design, two 100
F ceramic capacitors will be used at each
output.
C
IN1
and C
IN2
should be sized for a maximum current
rating of:
I
A
V
V
V
V
A
I
A
V
V
V
V
A
RMS
RMS
RMS
RMS
1
2
4
1 8
3 3
3 3
1 8
1 1 99
4
2 5
3 3
3 3
2 5
1 1 71
=
=
=
=
.
.
.
.
.
.
.
.
.
.
LTC3416
13
3416f
APPLICATIO S I FOR ATIO
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Decoupling the PV
IN
and SV
IN
pins with two 100
F capaci-
tors on both switching regulators is adequate for most
applications.
The resitor values for the voltage divider on V
OUT1
can be
calculated by using the following equation:
1 8
0 8
1
2
1
.
.
V
V
R
R
=
+
Setting R1 to 200k results in a value of 255k for R2. To
calculate the resistor values for the voltage divider on
V
OUT2
, we can use the following equations:
R
R
V
V
V
V
R
R
R
4
3
2 5
1 8
1
2 5
0 8
1
4
5
3
=
=
+
+
.
.
.
.
Setting R3 to 205k gives the following results: R4 = 78.7k
and R5 = 357k. Figure 6 shows the complete schematic for
this design example.
Figure 6. 1.8V and 2.5V, 4A Voltage Tracking Regulators at 1MHz
L2*
0.47
H
C
FF2
22pF
X7R
R5
357k
R4
78.7k
LTC3416
PV
IN
PV
IN
SV
IN
RUN
PGOOD
TRACK
R
T
SGND
PGND
PGND
SW
SW
SW
SW
V
FB
NC
NC
I
TH
PGND
PGND
7
14
16
4
17
3
2
5
1
10
8
9
12
13
19
6
15
18
20
11
C
ITH2
680pF
X7R
R3
205k
R
ITH2
5.9k
R
PG2
100k
R
OSC2
294k
C
IN2
**
100
F
2
V
IN
3.3V
PGOOD
C
OUT2
**
100
F
2
C
C2
22pF
X7R
V
OUT2
2.5V
4A
L1*
0.47
H
C
FF1
22pF
X7R
R2
255k
PV
IN
PV
IN
SV
IN
RUN
PGOOD
TRACK
R
T
SGND
PGND
PGND
SW
SW
SW
SW
V
FB
NC
NC
I
TH
PGND
PGND
7
14
16
4
17
3
2
5
1
10
8
9
12
13
19
6
15
18
20
11
C
ITH1
680pF
X7R
R1
200k
R
ITH1
5.9k
R
PG1
100k
R
OSC1
294k
TOKO FDVO630-R47M
TDK C4532X5R0J107M
*
**
C
IN1
**
100
F
2
V
IN
3.3V
PGOOD
C
OUT1
**
100
F
2
C
C1
22pF
X7R
3416 F06
V
OUT1
1.8V
4A
LTC3416
LTC3416
14
3416f
APPLICATIO S I FOR ATIO
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Figure 7. LTC3416 Layout Diagram
(7a) Top Layer
(7b) Bottom Layer
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3416. Check the following in your layout.
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected to
the PGND pin close to the LTC3416.
2. Connect the (+) terminal of the input capacitor(s), C
IN
,
as close as possible to the PV
IN
pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. You can connect the copper areas
to any DC net (PV
IN
, SV
IN
, V
OUT
, PGND, SGND or any
other DC rail in your system).
5. Connect the V
FB
pin directly to the feedback resistors.
The resistor divider must be connected between V
OUT
and SGND.
3416 F07a
3416 F07b
LTC3416
15
3416f
U
PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
FE20 (CA) TSSOP 0203
0.09 0.20
(.0036 .0079)
0
8
RECOMMENDED SOLDER PAD LAYOUT
0.45 0.75
(.018 .030)
4.30 4.50*
(.169 .177)
6.40
BSC
1
3
4
5
6 7 8
9 10
11
12
14 13
6.40 6.60*
(.252 .260)
4.95
(.195)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 0.15
(.002 .006)
0.65
(.0256)
BSC
0.195 0.30
(.0077 .0118)
2
2.74
(.108)
0.45
0.05
0.65 BSC
4.50
0.10
6.60
0.10
1.05
0.10
4.95
(.195)
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3416
16
3416f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
LT/TP 0104 1K PRINTED IN USA
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1.25A (I
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2.5A (I
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95% Efficiency, V
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3A (I
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Sink/source), 2MHz, Monolithic Synchronous
90% Efficiency, V
IN
: 2.25V to 5.5V, V
OUT
= V
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/2,
Regulator for DDR/QDR Memory Termination
I
Q
= 280
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SD
< 1
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4A (I
OUT
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60V, 2.75A (I
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600mA (I
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= 2.5V,
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I
Q
= 25
A, I
SD
< 1
A, MS Package
TYPICAL APPLICATIO
U
L1*
0.68
H
C2
22pF
X7R
R2
174k
PV
IN
PV
IN
SV
IN
RUN
PGOOD
TRACK
R
T
SGND
PGND
PGND
SW
SW
SW
SW
V
FB
NC
NC
I
TH
PGND
PGND
7
14
16
4
17
3
2
5
1
10
8
9
12
13
19
6
15
18
20
11
C
ITH
820pF
X7R
R1
200k
R
ITH
7.5k
R
PG
100k
R3
174k
R4
200k
R
OSC
294k
VISHAY DALE IHLP-2525CZ-01 0.68
H
TDK C4532X5R0J107M
*
**
C
IN1
**
100
F
V
IN
5V
PGOOD
C
OUT
**
100
F
2
C1
47pF
X7R
3416 TA01
V
OUT1
1.5V
4A
I/O SUPPLY
3.3V
LTC3416
1.5V, 4A Step-Down Regulator Tracking from 3.3V I/O Supply
Efficiency vs Load Current
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1
1
10
4316 TA02
30
20
10
0
90
100
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